The power supply in a conventional computer system is designed to be large enough to supply sufficient power needed by various computer chips of the computer system. Because of the rapid fluctuations in the power used by a computer chip, the power made available to each computer chip is generally maintained at a level that is higher than the average power used by the computer chip. This margin assures that the power used by the computer chip will always be less than the power made available to it.
FIG. 1 illustrates this principle. In FIG. 1, curve 110 represents the power used by a computer chip, and line 120 represents the power made available to the computer chip by the power supply. The space 130 between line 120 and curve 110 represents the excess power made available to the computer chip. It is desirable to minimize the space 130, as this would allow a smaller and thus a less expensive power supply to be used, or otherwise permit the computer chip to operate at higher power levels. However, doing so may increase the number of instances where the power used by the computer chip is greater than the power supplied to it. If line 120 represents the maximum power output of the power supply, such a condition, especially when sustained over a prolonged period of time, is likely to cause power failure.
Therefore, what is needed is a way to monitor the computer chip power usage and reduce its clock speed when its power usage exceeds the power made available to it so that the space 130 can be minimized. Analog, off-chip and on-chip power monitors are available in the prior art, but they are slow and add cost and complexity.